1. Field of the Invention
The present invention relates to a multiprocessor system, processor and interrupt control method.
2. Description of the Related Art
In an interrupt system of a controller or the like, an excellent real-time capability is required for system control. The reason for this is that if an interrupt corresponding to system control occurs and the time it takes for interrupt processing to end exceeds a preset time, a malfunction will occur in system control.
The real-time capability of a system is decided by the delay time of interrupt processing. Many causes of such delay are excessive interrupt-processing steps and interruption sources. Further, since a separate interrupt cannot be accepted during interrupt processing, the time from occurrence of the interrupt to the start of processing is prolonged.
Control of interrupt processing in a multiprocessor system is very complicated. In order to deal with multiple interrupts, therefore, often a dedicated CPU is decided in advance and interrupt processing is executed solely by the decided CPU. That is, often interrupt processing is assigned to a dedicated CPU even though all CPUs are capable of accepting interrupts as far as the hardware is concerned.
For these reasons, various proposals have been made with the aim of raising the speed of interrupt processing and affording versatility. Specific examples of such proposals will be described below.
A method of enhancing real-time capability in a multiprocessor system has been proposed (e.g. Japanese Patent Application Laid-Open No. 05-324569). According to this proposal, when a certain CPU attains the idle state, this CPU disables interrupt handling by other CPUs and handles all interrupts. Further, register values are set in such a manner that one or a plurality of CPUs executes interrupt processing per type of interrupt, and the CPU that will execute interrupt processing is selected.
With the method of Japanese Patent Application Laid-Open No. 05-324569, however, only an idle CPU is capable of acquiring an interrupt. If there is no CPU that is idle, therefore, then no CPU can acquire an interrupt. Further, register values are set in such a manner that one or a plurality of CPUs executes interrupt processing per interrupt type of all types. If the hardware configuration is changed or if the causes of interrupts increase or decrease, therefore, the register value settings and the number thereof required must also be changed. The result is lack of versatility.
Further, a method of enhancing real-time capability without being affected by an interrupt controller also has been proposed (e.g., U.S. Patent Application Laid-Open No. 2005/0193260). According to this proposal, interrupt tasks for processing respective interrupts are generated and interruption levels that have been decided with regard to interrupts processed by the interrupt tasks are reflected in the priorities of the interrupt tasks. When an interrupt is accepted, the interrupt task that handles the accepted interrupt is activated and control is transferred to a scheduler.
However, the proposal of U.S. Patent Application Laid-Open No. 2005/0193260 is such that if many interrupts having a high degree of priority occur, a large number of high-priority tasks are activated and real-time operation cannot be assured. Further, there is the possibility that low-priority interrupt processing will not be executed for long periods of time.